1. Field of the Invention
The present invention relates to the field of digital signal coding methods and apparatus.
2. Prior Art
Numerous signal coding techniques are well known for coding digital signals for transmission. Each coding technique typically has unique characteristics suitable for some applications, though perhaps not so desirable for other applications. By way of example, NRZ coding provides a very simple coding method, specifically, transmitting a signal for a first bit state and another signal for a second bit state. By way of example, NRZ coding usually codes a 0 by a low state signal and a 1 by a high state signal. The advantage of this coding is its simplicity, though a disadvantage is the fact that synchronization of the receiver takes special care if long strings of zeroes or ones are included in the transmission. Manchester coding, on the other hand, assures at least one transition per bit time, making synchronization of the receiver independent of long strings of zeroes or ones, though such coding has the disadvantage of having two transitions per bit time for strings of zeroes or ones, thereby requiring a wider band transmission medium for high speed communication. Both techniques generally require a phase locked loop (PLL) at the receiver for recovery and maintenance of the clock signal.
U.S. Pat. No. 6,317,469 discloses a method and apparatus for utilizing a data processing system for multi-level data communications providing self-clocking. That system uses single ended multiple voltage levels to represent different bit combinations and the clock signal, in the two embodiments disclosed in detail, different voltage levels (voltage ranges) represent the four possible combinations of two bits and a further voltage level or range to represent the clock signal. In one embodiment, a low voltage range represents the clock signal, a first voltage range above the clock signal represents the bit combination 00, a second voltage range above the first voltage range represents a bit combination of 01, a third voltage range above the second voltage range represents a bit combination of 10 and a voltage above the third voltage range represents a bit combination of 11. Thus for the transmission of two bits, the transmitted voltage increases to one of the applicable voltage ranges and then decreases into the clock signal voltage range before returning to the appropriate voltage range for transmission of the next two bit combination. In a second embodiment, the clock range is approximately mid-range, with separate voltage ranges for the same bit combinations above and as a mirror image below the clock voltage level. Here a single ended voltage swing upward to one of the voltage ranges above the clock range is indicative of the respective two bit combination, while a decrease through the clock voltage range to a lower voltage range is indicative of a following two bit combination. Accordingly, while in the first embodiment, the lower voltage range represented the clock signal, in this embodiment both the high and low voltage ranges provide two bit data combinations separated by a clock signal as the voltage passes through the clock signal range.